It is known from the paper “A Robust Self-calibrating Transmission Scheme for On-chip Networks”, by Frederick W Worm et al, November 2003 to provide on-chip networks in which operating parameters are adjusted based upon error detection with an automatic repeat request being issued when an error occurs so as to trigger the retransmission of the signals. This technique suffers from the disadvantage of having to provide a mechanism to communicate the need for retransmission of the signals as well as an impact upon system performance, in particular latency, associated with the retransmission.
A study of the relationship between energy reduction and reliability for on-chip communication has been published in the paper “Error Control Schemes for On-chip Communication Links: The Energy-Reliability Tradeoff” by Davide Bertozzi et al, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume 24, Number 6, June 2005. This paper compares the techniques of using error correction codes transmitted with the data and data retransmission for dealing with the transmission errors which occur as a consequence of measures to reduce energy consumption for the transmission, e.g. voltage reduction etc. The conclusion of Bertozzi is that retransmission is the preferred mechanism for dealing with such errors.
Benini L et al: “Networks on Chips: A new SOC Paradigm” Computer, vol. 35, no. 1, January 2002 discusses on-chip micronetworks, designed with a layered methodology, which will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components.
Beers G E et al: “A Novel memory bus driver/receiver architecture for higher throughput” VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on Chennai, India 4-7 Jan. 1998, IEEE Comput. Soc, US, 4 Jan. 1998 (1998-01-04), pages 249-264 describes a high-speed memory bus interface which enables greater throughput for data reads and writes is described in this paper. Current mode CMOS logic synthesis methods are used to implement multi-valued logic (MVL) functions to create a high bandwidth bus. First, a fundamental bi-directional data bus for multiple logic levels is presented. Then a bi-directional data bus with impedance matching terminators is presented. Finally a novel Adaptive Multi-Level Simultaneous bi-directional Transceiver (AMLST) bus structure for cache or main memory is proposed. The proposed bus can balance the memory channel bandwidth with the instruction execution rate of modern processors. Despite the problems encountered in implementing complete systems with MBL circuits, among which are circuit speed and design automation support, there is great potential in the future for this approach.
Zimmer H et al: “A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip” Codes+ISSS 2003. 1st IEEE/ACM/IFIP International Conference On Hardware/Software Codesign & System Synthesis. Newport Beach, Calif., Oct. 1-3, 2003, IEEE/ACM/IFIP International Coference on Hardware/Software Codesign & System Synthesis, New York, N, vol. CONF. 1, 1 October 2003 (2003-10-01), pages 188-193 proposes that the reliability of a Network-On-Chip will be significantly influenced by the reliability of the switch-to-switch connections. Faults on these buses may cause disturbances on multiple adjacent wires, so that errors on these wires can no longer be considered as statistically independent form one another, as it is expected due to deep submicron effects. A new fault model notation for buses is proposed which can represent multiple-wire, multiple-cycle faults. An estimation method based on this notation is presented which can accurately predict error probabilities. This method is used to examine bus encoding schemes. Finally, an encoding scheme for four Quality-of-Service classes is proposed which can be dynamically selected for each packet.